MANAV RACHNA UNIVERSITY
B. Tech Electronics & Communication Engineering (with Specialization in VLSI Design and Verification) in association with TrueChip – MRU
|COURSE FEES (Per annum) for Indian Nationals in Rupees||2,44000|
|COURSE FEES (Per annum) in US $ For PIO/NRI Students||US$ 5500|
|Criteria for Preparation of Merit list||Merit preparation/ short listing of candidates shall be on the basis of score in Pearson/ JEE Mains 2021/SAT/Uni Gauge E 2021/ MRNAT 2021/ XII Qualifying Examination|
|After 12th |
Pass in 10+2 examinations with at least 50% marks in aggregate in 5 subjects and eligibility shall be determined on the basis of percentage of aggregate marks in i. English, Physics & Mathematics and ii. One subject out of Chemistry, Computer Science, Biology or Biotechnology and iii. One subject with the highest score out of the remaining subjects.
For lateral Entry
50% marks in Diploma in Engineering in any branch/discipline of 3 year duration from State Board of Technical Education, Haryana or equivalent examination or B.Sc. Degree from a recognized University as defined by UGC with at least 50% marks and passed XII standard with Mathematics as a subject
Note: Manav Rachna now accepts Pearson Test Score for admission
The course is designed to give the student an understanding of the different design steps required to carry out a complete digital VLSI (Very-Large-Scale Integration) design and understand the concepts of Physical Design Process
- Bridge the gap between the Industry and Academia
- The students are job ready in the VLSI domain which includes Analog Layout Design, ASIC Design Verification, Physical Design, and DFT among many others.
Truechip, the Verification IP specialist, is a leading provider of Design and Verification solutions. Training Areas include HVL, HDL and Scripting, System Verilog (OVM, VMM, and UVM), Vera, Verilog, VHDL, Perl, C, C++, Unix shell scripting and automation. Students will work on the following tools:
Front End EDA Tools for Design and Verification:
Cadence -Verilog-XL, NC-Verilog
Synopsys – VCS,
Mentor – Questa, Modelsim, FPGA Synthesis: Precision, Synplify & ISE, Spyglass,
Back End EDA Tools for Physical Design of the circuit:
Cadence – RC, GPS, Nanroute, ETS,
Synopsys – DC, ICC, PT-SI, Tetramax.
- Students who are enrolled in the course will have 20 modules designed by Truechip and Futurewiz based upon the current industrial requirements.
- Hands-on training from industry experts on industry-leading tools from Mentor Graphics/ Cadence/Synopsys Tools with Verilog, System Verilog and UVM based Training
- After successful completion of the training course will be provided placement opportunities in VLSI/ EDA/ Semiconductor companies based upon the eligibility criteria.
- All students who successfully complete the course of 20 modules, will be issued certificates of course completion.
- Confirmed Employment Program for VLSI Design, with average Package: 4 Lakhs per annum.
ST Micro Electronics, Freescale, Cadence, TrueChip, Mentor Graphics