The Department of ECE successfully organized a workshop on “Design and Verification of Digital Systems using Verilog HDL” from 21st Feb. to 22nd Feb, 2018 by Truechip& FUTUREWIZ.
The two days workshop was organized with the idea of exposing the students as well as faculty to the industrial application aspects of VLSI.
Truechip, the Verification IP specialist, is a leading provider of Design and Verification solutions – which helps in, accelerating design, lowering the cost and the risks associated with the development of your ASIC, FPGA, and SOC. FUTUREWIZ is a VLSI Design academy’ an offshoot of Truechip Solutions, a renowned name in Verification IP Design technologies. Futurewiz USP lies in being able to deliver comprehensive yet customized courses that improve proficiency on basic concepts as well as advanced tools and methodologies. Futurewiz also provides training to corporate for their better development as well as knowledge growth.
The facilitators for the workshop were
- Mr. Abhinav Kumar (Design verification Engineer & Trainer)
- Mr. Saurabh Gupta(Design verification Engineer)
- Mr. Vishwajeet Nayak(Design verification Engineer) (Alumnae of MRU)
- Mr. Ranveer Singh (Assistant Marketing Head) (Alumnae of MREI)
The session started with basic knowledge of VLSI industry, Chip Design, SOC (System On Chip) ,IC Technology & scope of VLSI. Moving forward with Basic Concepts (Data Types, Module, Instance, Operators, Modeling etc.) and implementation concepts of VERILOG HDL.
The workshop focused on hands on practice on XILINX TOOL with Spartan FPGA board. This workshop as a whole to learn the design concepts used in real life applications. The workshop also threw light on the troubles encountered when the theoretical concepts are used in real life applications. The alternate solutions were discussed.
The participants kept the live atmosphere through their active participation. All the participants showed their enthusiasm by expressing interest in gaining knowledge through such workshops.